Zpět na vyhledávání.CPL Jobs s.r.o - ASIC/FPGA Engineer
| Typ zaměstnání : | Permanent |
| Umístění : | Brno - Jihomoravsky, Czech Republic, Brno |
| Plat : | 1000-1500 |
| Jazyky : | Anglický |
Podrobnosti o inzerentovi
- Jméno :CPL Jobs s.r.o
- Uveřejněno :01-04-2012
- kód:YVK158
ASIC/FPGA Engineer
Responsibilities:
This position will be part of a design team designing and developing FPGAs and ASICs. The candidate will be expected to work on a team with other engineers developing complex devices.
Also this candidate should be able to work independently or lead a small group of engineers through a project. This engineer will be responsible to complete assigned tasks on schedule. Typical tasks include, HDL coding, running simulations, synthesis, creating test benches, and doing documentation. Candidates must be extremely reliable and must conform to process standards.
Requirements:
• Master degree in Electrical Engineering, Computer Science
• Solid knowledge of digital design
• Good knowledge of VHDL and Verilog
• Able to use Linux or Unix workstations
• Knowledge of the ASIC/FPGA design tools: simulators, STA tools, synthesis, etc.
• Able to work in a team environment and coordinate the work of others
• Communicative knowledge of English
• Strong computer and web navigation skills required (Word, Excel, PowerPoint, Internet Explorer)
• Strong organizational and problem solving skills
Responsibilities:
This position will be part of a design team designing and developing FPGAs and ASICs. The candidate will be expected to work on a team with other engineers developing complex devices.
Also this candidate should be able to work independently or lead a small group of engineers through a project. This engineer will be responsible to complete assigned tasks on schedule. Typical tasks include, HDL coding, running simulations, synthesis, creating test benches, and doing documentation. Candidates must be extremely reliable and must conform to process standards.
Requirements:
• Master degree in Electrical Engineering, Computer Science
• Solid knowledge of digital design
• Good knowledge of VHDL and Verilog
• Able to use Linux or Unix workstations
• Knowledge of the ASIC/FPGA design tools: simulators, STA tools, synthesis, etc.
• Able to work in a team environment and coordinate the work of others
• Communicative knowledge of English
• Strong computer and web navigation skills required (Word, Excel, PowerPoint, Internet Explorer)
• Strong organizational and problem solving skills
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